1. Technical Field
The present invention generally relates to a semiconductor apparatus, and more particularly, to a delay circuit which delays a cock and a command signal and a semiconductor apparatus including the same.
2. Related Art
In general, a semiconductor apparatus including a memory performs an operation in synchronization with a clock. Accordingly, in a synchronous type semiconductor apparatus, input data, and output data should be precisely synchronized with an external clock. The semiconductor apparatus receives the external clock, converts the external clock into an internal clock, and uses the converted internal clock. However, as the internal clock is transmitted through a clock buffer and a transmission line, a phase difference occurs between the internal clock and the external clock. Therefore, in order to compensate for the phase difference, the semiconductor apparatus generally includes a phase-locked loop or a delay-locked loop.
Further, the semiconductor apparatus performs an internal data processing operation by synchronizing a command inputted in synchronization with the external clock, with the internal clock. Thus, a domain crossing operation for synchronizing the command synchronized with the internal clock, with the external clock is performed.
FIG. 1 is a block diagram showing the configuration of a conventional semiconductor apparatus 10. In FIG. 1, the semiconductor apparatus 10 includes a clock delay line 11, a first shift register 12, a delay modeling block 40, a phase detection block 30, and a delay line control block 20. The clock delay line 11 receives an input clock CLKI, delays the input clock CLKI by a preset delay value, and generates a delayed clock CLKD. The delay modeling block 40 delays the delayed clock CLKD by a modeled delay value and generates a feedback clock CLKF.
The phase detection block 30 compares the phases of the input clock CLKI and the feedback clock CLKF. The delay line control block 20 generates a control signal CTRL for controlling the first shift register 12, according to a phase comparison result of the phase detection block 30. The first shift register 12 receives the control signal CTRL and may set the delay value of the clock delay line 11.
Also, the semiconductor apparatus 10 further includes a command delay line 51, a second shift register 52, a clock driver 60, and an output enable signal generation block 70. The second shift register 52 sets the delay value of the command delay line 51 in response to the control signal CTRL. The command delay line 51 delays a command signal CMD by a preset delay value and generates a delayed command signal CMDD. The command delay line 51 may have the same configuration as the clock delay line 11. The clock driver 60 receives the delayed clock CLKD and generates a data clock CLKDQS. The output enable signal generation block 70 generates an output enable signal OUTEN according to the delayed clock CLKD, the delayed command signal CMDD and CAS latency information CL.
As can be seen from FIG. 1, the clock delay line 11 and the command delay line 51 have the same configuration and are controlled by the same control signal CTRL. That is to say, the first shift register 12 for setting the delay amount of the clock delay line 11 and the second shift register 52 for setting the delay amount of the command delay line 51 commonly receive the control signal CTRL which is outputted from the delay line control block 20. In this way, in the conventional semiconductor apparatus, a plurality of delay lines with the same delay value respectively have shift registers.